Projects
Hardware and software, side by side: Java design patterns, a Verilog processor, a Node.js + Claude API assistant, and a retrieval-augmented generation engine built from scratch. Every project links to the code.
A Romanian-language AI assistant built on the Claude API. Express 5 + PostgreSQL backend that persists conversations; switch between Claude models mid-chat. Live demo available.
Node.js · Express 5 · PostgreSQL · Claude API · Vercel
JavaScript · updated Jun 2026 · Code · Live demo
A three-level 2D puzzle game (AWT/Swing) built as a study in GoF design patterns — Singleton, Flyweight, Abstract Factory — with MariaDB persistence. Built with a teammate; gameplay GIFs on the project page.
Java · AWT/Swing · MariaDB · GoF patterns
Java · updated Jul 2026 · Code
Multicycle RISC-V Processor
A multicycle RISC-V processor implemented in Verilog: FSM-based control path, full datapath (ALU, register file, unified memory), and custom instructions added end-to-end — from opcode decoding to new FSM states. Simulated and verified in Vivado.
Verilog · Vivado · RISC-V ISA
RAG-core — Retrieval-Augmented Generation from scratch
A from-scratch RAG implementation in Python — no framework shortcuts: document chunking, embeddings, retrieval, and generation wired together by hand to understand how the pieces actually fit.
Python
Python · updated Jun 2026 · Code
NXP Cup — Autonomous Line-Following Car
Competition entry: an autonomous car on an S32K144 MCU, programmed in bare-metal C++ with PID control and a Pixy camera for line detection. Built with a teammate for the NXP Cup.
C++ (bare-metal) · S32K144 · PID · Pixy camera